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We present a methodology in which the behavior of a switch level device is specified using abstract parameterized regular expressions. These specifications are used to generate a finite automaton representing an abstraction of the...
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We present a methodology in which the behavior of a switch level device is specified using abstract parameterized regular expressions. These specifications are used to generate a finite automaton representing an abstraction of the behavior of a block of memory comprised of a set of such switch level devices. The automaton, in conjunction with an Efficient Memory Model [1], [2] for the devices, forms a symbolic simulation model representing an abstraction of the array core embedded in a larger design under analysis. Using Symbolic Trajectory Evaluation, we check the equivalence between a register transfer level description and a schematic description augmented with abstract specifications for one of the custom memories embedded in the MPC7450 PowerPC processor.
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This paper describes a structurally-guided framework for the decomposition of a verification task into subtasks, each solved by a specialized algorithm for overall efficiency. Our contributions include the following: (1) a structu...
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This paper describes a structurally-guided framework for the decomposition of a verification task into subtasks, each solved by a specialized algorithm for overall efficiency. Our contributions include the following: (1) a structural algorithm for computing a bound of a state-transition diagram's diameter which, for several classes of netlists, is sufficiently small to guarantee completeness of a bounded property check; (2) a robust backward unfolding technique for structural target enlargement: from the target states, we perform a series of compose-based preimage computations, truncating the search if resource limitations are exceeded; (3) similar to frontier simplification in symbolic reachability analysis, we use induction via don't cares for enhancing the presented target enlargement. In many practical cases, the verification problem can be discharged by the enlargement process; otherwise, it is passed in simplified form to an arbitrary subsequent solution approach. The presented techniques are embedded in a flexible verification framework, allowing arbitrary combinations with other techniques. Extensive experimental results demonstrate the effectiveness of the described methods at solving and simplifying practical verification problems.
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With memory safety and security issues continuing to plague modern systems, security is rapidly becoming a first class priority in new architectures and competes directly with performance and power efficiency. The capability-based...
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With memory safety and security issues continuing to plague modern systems, security is rapidly becoming a first class priority in new architectures and competes directly with performance and power efficiency. The capability-based architecture model provides a promising solution to many memory vulnerabilities by replacing plain addresses with capabilities, i.e., addresses and related metadata. A key advantage of the capability model is compatibility with existing code bases. Capabilities can be implemented transparently to a programmer, i.e., without source code changes. Capabilities leverage semantics in source code to describe access permissions but require customized compilers to translate the semantics to their binary equivalent.In this work, we introduce a complete capabilityaware compiler toolchain for such secure architectures. We illustrate the compiler construction with a RISC-V capability-based architecture, called Zeno. As a securityfocused, large-scale, global shared memory architecture, Zeno implements a Namespace-based capability model for accesses. Namespace IDs (NSID) are encoded with an extended addressing model to associate them with access permission metadata elsewhere in the system. The NSID extended addressing model requires custom compiler support to fully leverage the protections offered by Namespaces. The Zeno compiler produces code transparently to the programmer that is aware of Namespaces and maintains their integrity. The Zeno assembler enables custom Zeno instructions which support secure memory operations. Our results show that our custom toolchain moderately increases the binary size compared to nonZeno compilation. We find the minimal overhead incurred by the additional NSID management instructions to be an acceptable trade-off for the memory safety and security offered by Zeno Namespaces.
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Precisely controlled power delivery is critical for high performance systems-on-chip. This work describes functional test sequences to induce large dynamic and static supply voltage droops impacting the minimum operating voltage (...
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Precisely controlled power delivery is critical for high performance systems-on-chip. This work describes functional test sequences to induce large dynamic and static supply voltage droops impacting the minimum operating voltage (V
MIN
) of the processor. An algorithm is provided to generate high and low power sequences that are functions targeting a wide range of power delivery network (PDN) frequencies. The voltage-droop tests induce large dynamic voltage droops by aligning hardware threads using a method that generates relatively prime sequence lengths across threads in a multi-threaded processor system. Functional tests also create symmetric and asymmetric high and low power sequences, introducing delay in processor pipeline stages. Additionally, tests consisting of a loop of sustained high-power sequences are also generated causing static droops. Simulation and silicon results of voltage-droop tests applied on a multi-threaded Qualcomm
?
Hexagon
?
processor show that the techniques increase the V
MIN
of the processor system by up to 120 mV. Evaluation of the relatively prime method against the previously published NOP insertion method shows that the sequences generated using the relatively prime method can induce a higher rate of change of maximum dynamic voltage droop in $\sim 72.5$% of functional test sequences.
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摘要 :
Precisely controlled power delivery is critical for high performance systems-on-chip. This work describes functional test sequences to induce large dynamic and static supply voltage droops impacting the minimum operating voltage (...
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Precisely controlled power delivery is critical for high performance systems-on-chip. This work describes functional test sequences to induce large dynamic and static supply voltage droops impacting the minimum operating voltage (V
MIN
) of the processor. An algorithm is provided to generate high and low power sequences that are functions targeting a wide range of power delivery network (PDN) frequencies. The voltage-droop tests induce large dynamic voltage droops by aligning hardware threads using a method that generates relatively prime sequence lengths across threads in a multi-threaded processor system. Functional tests also create symmetric and asymmetric high and low power sequences, introducing delay in processor pipeline stages. Additionally, tests consisting of a loop of sustained high-power sequences are also generated causing static droops. Simulation and silicon results of voltage-droop tests applied on a multi-threaded Qualcomm
®
Hexagon
™
processor show that the techniques increase the V
MIN
of the processor system by up to 120 mV. Evaluation of the relatively prime method against the previously published NOP insertion method shows that the sequences generated using the relatively prime method can induce a higher rate of change of maximum dynamic voltage droop in $\sim 72.5$% of functional test sequences.
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Recently neural network accelerators have grown into prominence with significant power and performance efficiency improvements over CPU and GPU. In this paper, we proposed two safety design techniques include Algorithm Based Atomi...
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Recently neural network accelerators have grown into prominence with significant power and performance efficiency improvements over CPU and GPU. In this paper, we proposed two safety design techniques include Algorithm Based Atomic Error Checking-1 (ABAEC-1) and ABAEC-2 for a Weight Stationary (WS) Convolutional Neural Network (CNN) accelerator focusing on low latency and low overhead error detection and correction with no performance degradation. The proposed design techniques not only detect the errors on-the-fly but also perform error diagnosis to localize the errors to a Processing Element (PE) for on-line fault management and recovery. We applied the design techniques on an industry quality CNN accelerator and demonstrated that we could achieve the required Diagnostic Coverage (DC) goal with minimal area and power overhead for selected configurations. Furthermore, we discussed methods to extend the proposed techniques to other dataflow architecture.
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摘要 :
Recently neural network accelerators have grown into prominence with significant power and performance efficiency improvements over CPU and GPU. In this paper, we proposed two safety design techniques include Algorithm Based Atomi...
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Recently neural network accelerators have grown into prominence with significant power and performance efficiency improvements over CPU and GPU. In this paper, we proposed two safety design techniques include Algorithm Based Atomic Error Checking-1 (ABAEC-1) and ABAEC-2 for a Weight Stationary (WS) Convolutional Neural Network (CNN) accelerator focusing on low latency and low overhead error detection and correction with no performance degradation. The proposed design techniques not only detect the errors on-the-fly but also perform error diagnosis to localize the errors to a Processing Element (PE) for on-line fault management and recovery. We applied the design techniques on an industry quality CNN accelerator and demonstrated that we could achieve the required Diagnostic Coverage (DC) goal with minimal area and power overhead for selected configurations. Furthermore, we discussed methods to extend the proposed techniques to other dataflow architecture.
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摘要 :
Recently neural network accelerators have grown into prominence with significant power and performance efficiency improvements over CPU and GPU. In this paper, we proposed two safety design techniques include Algorithm Based Atomi...
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Recently neural network accelerators have grown into prominence with significant power and performance efficiency improvements over CPU and GPU. In this paper, we proposed two safety design techniques include Algorithm Based Atomic Error Checking-1 (ABAEC-1) and ABAEC-2 for a Weight Stationary (WS) Convolutional Neural Network (CNN) accelerator focusing on low latency and low overhead error detection and correction with no performance degradation. The proposed design techniques not only detect the errors on-the-fly but also perform error diagnosis to localize the errors to a Processing Element (PE) for on-line fault management and recovery. We applied the design techniques on an industry quality CNN accelerator and demonstrated that we could achieve the required Diagnostic Coverage (DC) goal with minimal area and power overhead for selected configurations. Furthermore, we discussed methods to extend the proposed techniques to other dataflow architecture.
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With the advent of high performance computing platforms and design automation tools there has been a migration from physical prototyping of VLSI systems to virtual prototyping in both the industrial and educational environments. T...
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With the advent of high performance computing platforms and design automation tools there has been a migration from physical prototyping of VLSI systems to virtual prototyping in both the industrial and educational environments. This move is attractive for many educational institutions as it is possible to have a "virtual" lab environment for a wide range of the curriculum that requires only computers and EDA software. This shift to virtual prototyping as the preferred method for teaching the design of integrated circuits and systems offers quicker iteration and exploration, but it leaves significant gaps in the intuitive and systematic design competencies gained from physically implementing and testing a complex electronic system. We have attempted to strike a balance between the two approaches, and this paper analyzes the lessons learned from our use of a common set of virtual and physical prototyping platforms for a four course graduate sequence in integrated circuit design and embedded system-on-chip (SoC) design.
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Effective and meaningful visualization techniques are quite important for multidimensional DNA microarray gene expression data analysis. Elucidating the cluster properties of these multidimensional data are often complex. Patterns...
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Effective and meaningful visualization techniques are quite important for multidimensional DNA microarray gene expression data analysis. Elucidating the cluster properties of these multidimensional data are often complex. Patterns, hypotheses on the relationships, and ultimately of the function of the gene can be analyzed and visualized by non-linear reduction of the multidimensional data to a lower dimension. In this paper, an improved SOM visualization technique named Improved Side Intensity Modulated (ISIM) Self-Organizing Map (SOM) has been proposed and compared with other SOM based visualization techniques. On different datasets, ISIM-SOM is found to offer better cluster boundary, simplicity and clarity.
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